Modern communications technologies rely on the ability of equipment to quickly and efficiently convert data between analog and digital formats. As a result, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) have become central components in a wide variety of applications. As these applications have become increasingly sophisticated, the demand for greater bandwidth and resolution from their ADCs and DACs has risen dramatically.
At a high level, an ADC receives an analog signal and produces a digital signal and a DAC receives a digital signal and produces an analog signal. In an ADC, the digital signal comprises a sequence of discrete quantized values that, over time, track the parameter variations of the analog signal. Quantization error is an unwanted byproduct of this quantization process. DAC and ADC are characterized by their sampling frequency and degree of resolution. The ability of a converter to digitize an analog signal faithfully is a direct function of both of these parameters. As the sampling frequency is increased, the analog signal is sampled at more points in time. As the degree of resolution is refined, differences between the digital signal and analog signal are minimized.
Many distinct architectures exist for DACs and ADCs including “flash,” “pipelined,” “successive approximation,” and “sigma delta” architectures. Each architecture has benefits and drawbacks. Paramount among these is a tradeoff between bandwidth and degree of resolution. Of these architectures, sigma delta converters have exhibited the best balance between bandwidth and resolution.
A conventional sigma delta converter includes a sigma delta modulator followed by a decimator. The sigma delta modulator samples the input signal at a rate that is much faster than the Nyquist rate. The use of oversampling combined with noise shaping functionality allows a sigma delta modulator to move most of the quantization noise outside the band of the signal. The decimator then reduces the frequency of the resultant output and filters the out of band noise.
FIG. 1 illustrates a conventional first-order, single-stage, single-bit sigma delta modulator 100. A sigma delta modulator can be included in either a ADC or a DAC. In addition, a sigma delta modulator can have either an analog or a digital implementation. A single converter can contain an analog or digital sigma delta modulator or both. Sigma delta modulator 100 includes a summing node 110, an integrator 120, a single-bit quantizer 150, and a converter 160. Summing node 110, integrator 120, and quantizer 150 are connected, respectively, in series along signal path 108. Converter 160 is connected in parallel with signal path 108 between node N0 104 and summing node Σ0 110.
Initially, a signal x[n] passes through summing node 110 and is sampled by integrator 120. Integrator 120 integrates signal x[n] over a given period of time to produce an integrated signal v[n]. Integrated signal v[n] is transmitted to single-bit quantizer 150. Single-bit quantizer 150 rounds integrated signal v[n] to the closest of two preset levels (i.e., a single bit) to produce a quantized signal y[n]. To minimize the difference between quantized signal y[n] and signal x[n], quantized signal y[n] is transmitted to converter 160 and converted to produce an feedback signal fbk[n], which is fed back to summing node 110.
At summing node 110, feedback signal fbk[n] is subtracted from signal x[n] to produce an difference signal u[n]. Difference signal u[n] passes into integrator 120 and the process described above is repeated. Essentially, integrator 120 integrates the difference between quantized signal y[n] and signal x[n]. Over a large number of samples, integrator 120 forces this difference to approach zero. Thus, signal x[n] is received by modulator 100 and converted into quantized signal y[n], produced at node N0 104. The quantized signal y[n] comprises a stream of quantized values. Typically, this stream is produced at a modulator frequency that is several times greater than the carrier frequency of analog signal x[n]. The ratio of the modulator frequency to the Nyquist frequency is referred to as the oversampling ratio.
Signal-to-noise ratio (SNR) is an important measurement in a sigma-delta converter because a higher SNR translates into smaller distortion between digital and analog signals. In a sigma delta modulator, the SNR improves when the oversampling ratio is increased. For example, as a “rule of thumb,” the SNR for an ADC improves by 9 dB for every doubling of its oversampling ratio. The use of high-order sigma delta modulators further improves the SNR. As a result, high-order single-loop sigma delta modulators are desirable for high SNR applications such as digital voice and audio.
High-order sigma delta modulators can be implemented using a wide variety of architectures. For example, a sigma delta modulator could have either a single stage or cascaded (also known as MASH) architecture. In a cascaded architecture, two or more low-order sigma delta modulators are coupled to produce a high-order sigma delta modulator. A modulator is considered high-order if it contains 3 or more integrator segments. A detailed explanation of the various high-order architectures is provided in the book “Delta-Sigma Data Converters—Theory, Design and Simulation,” Norsworthy et al., IEEE Press, Piscataway, N.J. (1997), which is incorporated herein by reference in its entirety.
A high-order single stage single-loop sigma delta modulator can either follow a multiple feed forward topology or a multiple feedback topology. FIG. 2 is a block diagram of a third-order single-loop sigma delta modulator 200 having a multiple feed forward topology. Modulator 200 has a first summing node 210, a first integrator 220, a second integrator 230, a third integrator 240, a second summing node 212, and a quantizer 150 connected, respectively, in series along signal path 208. A first amplifier 272 is connected in parallel with signal path 208 between node N1 206 and the second summing node 212. A second amplifier 274 is connected in parallel with signal path 208 between node N2 207 and the second summing node 212. A third amplifier 276 is connected in parallel with signal path 208 between node N0 104 and the first summing node 210.
Referring to FIG. 2, signal x[n] passes through the first summing node 210 and is sampled by the first integrator 220. First integrator 220 produces an integrated signal v1[n]. Integrated signal v1[n] is transmitted to second integrator 230 and to first amplifier 272. First amplifier amplifies the signal by c1 and generates signal vc1[n]. The second integrator 230 integrates signal v1[n] over a given period of time to produce an integrated signal v2[n]. Integrated signal v2[n] is transmitted to third integrator 240 and to second amplifier 274. Second amplifier 274 amplifies the signal by c2 and generates signal vc2[n]. The third integrator 240 integrates the signal v2[n] over a given period of time to produce an integrated signal v3[n].
At the second summing node 212, integrated signal v3[n] is added to amplified signals vc1[n] and vc2[n] resulting in signal w[n]. Signal w[n] is input to single-bit quantizer 150. Single-bit quantizer 150 produces a quantized signal y[n]. Quantized signal y[n] is transmitted to third amplifier 276 and amplified by C3 to produce a feedback signal fbk[n], which is fed back to the first summing node 210. At the first summing node 210, feedback signal fbk[n] is subtracted from signal x[n] to produce a difference signal u[n]. Difference signal u[n] passes into the first integrator 220 and the process described above is repeated.
FIG. 3 is a block diagram of a third-order single-loop sigma delta modulator 300 having a multiple feedback topology. Modulator 300 comprises a first summing node 310, a first integrator 320, a first amplifier 372, a second summing node 314, a second integrator 330, a second amplifier 374, a third summing node 316, a third integrator 340, and a quantizer 150 connected, respectively, in series along signal path 308. A gain amplifier 378 is connected in parallel with signal path 308 between node N1 and the second summing node 314. A third amplifier 376 is connected in parallel with signal path 308 and feds back a signal to the first, second, and third summing nodes 310, 314, 316.
The integrators shown in FIG. 1 through 3 can either be digital integrators or analog integrators. Many architectures exist for implementing analog and digital integrators. FIG. 4A is a block diagram illustrating an exemplary architecture for a conventional digital integrator 420. Digital integrator 420 comprises an adder 422 and a delay 424. The delayed output of the adder 422 is fed back to the adder 422 along signal path 426.
Conventional analog integrators are typically implemented using either a switch-capacitor or a continuous time design. FIG. 4B illustrates an exemplary switch-capacitor analog integrator 430. Integrator 430 includes an operational amplifier (op amp) 432, a first capacitor 434, a second capacitor 436, phase 1 switches S1 and S4, and phase 2 switches S2 and S3. Switch S1, first capacitor 434, and Switch S4 are connected, respectively, in series between the input of the integrator and the inverting (negative) terminal of op amp 432. Second capacitor 436 is connected between the inverting terminal of op amp 432 and the op amp output. Switch S2 is connected between N1 and ground. S4 is connected between N2 and ground.
The 3rd order single-loop sigma-delta modulators shown in FIG. 2 and FIG. 3 achieve 14-bit resolution with an oversampling ratio of 40. The multiple feedback topology of FIG. 3 is especially useful for digital sigma-delta modulation since the one-bit feedback could make its implementation multiplier free. Notwithstanding these benefits, all high-order sigma delta modulators are susceptible to instability. When a large signal is received as input to the modulator, the internal filter states of the modulator exhibit large signal oscillation. The modulator then produces an output of alternating long strings of 1's or 0's. The signal-to-noise-plus-distortion ratio (SNDR) drops dramatically when the sigma delta modulator is operating in an unstable state. A detailed explanation of the stability problem is provided in the book “Delta-Sigma Data Converters—Theory, Design and Simulation,” Norsworthy et al., referenced above.
A current technique for addressing the stability problem is the integrator reset technique. This technique is frequently used when an analog switch capacitor integrator is built using CMOS technology. In this technique, the modulator determines when instability exists and triggers a short pulse to reset the integrator. One method for determining the existence of instability is through the use of a comparator. In another method, modulator instability is detected when a sufficiently long string of 1's or 0's occurs at the output of the modulator. When instability is detected, the integrator is reset with a short pulse. If the frequency of the reset event is lower than the cut-off frequency of the subsequent filter, a large amount of noise may appear at the output of the modulator.
Another current technique for addressing the stability problem is the state-variable clamping technique. In the state-variable clamping technique, a limiter is placed in the forward path of the integrator. FIG. 5A depicts a block diagram of an analog integrator 3530 implementing the state variable stabilizing technique. Analog integrator 530 comprises an op amp 532, a capacitor 536, a limiter 538, and a resistor 533. Limiter 538 has thresholds of +V and −V. When the voltage across capacitor 536 exceeds the limiting voltage threshold, the output of the integrator clamps. Since the output voltage cannot go to the rail, the op amp 532 keeps in the linear region of operation and stability improves.
FIG. 5B depicts a block diagram of a digital integrator 520 implementing the state variable stabilizing technique. The digital integrator 520 comprises an adder 522, a delay 524, and a limiter 528. Similar to the analog integrator 530, the output of the digital integrator is clamped to the limiter value when the input exceeds the limiting threshold. A drawback of the state-variable clamping technique is that the signal path is blocked when the signal level exceeds a certain level, resulting in significantly deteriorated SNDR for large signals.
The current state-variable clamping technique described above is viable for the multiple feed-forward topology illustrated in FIG. 2 where the last integrator is limited in the forward path. When the last integrator degrades into DC, two other feed-forward paths still exist to the output. Thus, when the limiter in the third integrator is active, the 3rd order sigma delta modulator shown in FIG. 2 degrades into a 2nd order sigma delta modulator. The 2nd order sigma delta modulator is stable but it has a lower SNDR. However, this limiting method is not appropriate for the multiple feedback topology shown in FIG. 3. In this topology, when the third integrator degrades to DC and blocks the forward path, no more signal paths to the output of the modulator exist.
A need therefore exists for an integrator that can improve the SNDR when a high-order sigma delta modulator becomes unstable without blocking the input signal path or degrading the input signal into a DC signal.